1. Field of the Invention
This invention relates generally to a method for forming polysilicon structures in semiconductor devices and more specifically to an improved process for forming tapered polysilicon structures.
2. Description of the Prior Art
Typically, high-capacity dynamic random access memory (DRAM) cell structures are fabricated on a semiconductor chip having many thousands of similar cells and successful operation of the chip requires that all such cells be free of defects. However, the standard process for forming DRAM cells in an array frequently results in an unwanted structure that shorts the transfer gates in two adjacent memory cell structures.
This problem is best understood by considering the fabrication steps used to form prior art DRAM cells on a semiconductor chip. Only the processing steps related to the failure mechanism are described herein. The other processing steps are known to those skilled in the art. As shown in FIG. 1, the substrate is typically overlain by a thin dielectric region 12. For example, dielectric region 12 may consist of a thin silicon oxide layer 12A, typically about 50 .ANG. thick, which is formed on substrate 10, and in turn covered by a silicon nitride layer 12B, typically about 100 .ANG. thick. After formation of silicon nitride layer 12B, polysilicon layer 14 is formed which in turn is overlain by a sacrificial oxide layer 15.
After formation of oxide layer 15, a photoresist mask 17 (FIG. 2) is formed on oxide layer 15 with opening 17-3 that is used to define the extent of the capacitance electrode in the DRAM cell. As oxide layer 15 (FIG. 2) is etched, photoresist mask 17 is undercut as shown in FIG. 3. Photoresist mask 17 is subsequently stripped using a wet etch process leaving the structure illustrated in FIG. 4.
Etched oxide layer 15 is used as a mask for a wet etch of capacitance polysilicon layer 14 to form the structure shown in FIG. 5. Sacrificial oxygen layer 15 is then removed to leave the structure of FIG. 6.
The shape of edge surface 14C of capacitance plate 14 was formed by the wet etch of capacitance polysilicon layer 14 and angle .gamma. between bottom surface 14A of electrode 14 and edge surface 14C is determined by the etching process. Angle .gamma. is typically in the range of about 90.degree. to about 60.degree. with a typical angle being about 80.degree..
The steep inclination of edge surface 14C is one factor that limits the yield of prior art DRAM cells. Oxide layer 16 is subsequently formed on polysilicon layer 14. Oxide layer 16 typically forms a protruding lip 16A as shown in FIG. 7. Lip 16A is the structure which directly contributes to creation of one failure mechanism for a DRAM cell. Lip 16A extends around the perimeter of elliptical opening 28 (FIG. 7).
After formation of oxide layer 16, a triple-etch, using oxide layer 16 as a mask, is used to remove dielectric layers 12A, 12B between oxide layer 16-1, 16-2 so that surface 10.sub.1 of substrate 10 is exposed. Gate oxide 20 is grown on surface 10.sub.1, and then the entire structure is overlain by a polysilicon layer 18A (FIG. 8). A mask and a plasma etch are typically used to form gates 18-1, 18-2 (FIG. 9) from polysilicon layer 18A. However, the plasma etch fails to remove polysilicon 18B under lip 16A because the plasma etch is shielded from this area by lip 16A.
Accordingly, gate structures 18-1, 18-2 are connected by polysilicon 18B (FIG. 10) and the associated DRAM cells are electrically shorted through gate 18.
Hence, the steep inclination of edge surface 14C of capacitance polysilicon results in protruding lip 16A being formed in overlying oxide layer 16 which in turn results in a failure mechanism for the associated DRAM cell. This failure mechanism is a function of the prior art processing steps so that to obtain increased yield, two additional processing steps are required. Removal of polysilicon 18B requires another mask step and an isotropic etch so as to break polysilicon 18B in two places. These additional processing steps while increasing yields also increase processing costs and processing times.